A typical semiconductor random access memory device (e.g., a static random-access memory (“SRAM”), includes word lines, bit lines, and a memory array of cells with cell latches and pass devices connected at intersections between the word lines and the bit lines. The pass devices of the memory cells are connected to the bit lines. During a read or write operation, the bit lines allow the contents of the memory cell to be successfully read from or written into a cell latch by activating a particular word line coupled to the cell latch.
In order to test the memory device, a memory array bypass function is required to enable testing of upstream and downstream logic paths to and from the memory device without accessing the memory contents in the memory array. Array bypass logic can take data input D and propagate that data D to a data output Q without having to be written to the memory array.
FIG. 1 illustrates a prior art memory device having an asynchronous write-through circuitry for testing the memory device. A memory device of the prior art comprises a bitcell array 40, a write-driver 42, AND gates 44 and 46, an inverter 48, latches 50 and 54, a sense amplifier 52, and a multiplexer 56. The bit cell array 40 can have memory cells that have word lines which can be activated by a word line signal. The word lines can be further coupled to the bit lines for writing to the word lines or reading from the word lines. For instance, a data input D can be written to the bit cell array 40 by being stored at the latch 50 and then propagated to the bit lines via the inverter 48, the AND gates 44 and 46, and the write driver 42. A data output Q can be read back by sensing a current or voltage level of the bit lines by the sense amplifier 52. The sensed current or voltage can then be stored by the latch 54 for output.
The multiplexer 56 can serve as a logic bypass so that testing can be performed without having to write or read to the bit cell array 40. For instance, if a logic_test signal indicates that a test mode is activated, then the inputted test data D can be selected by the multiplexer 56 for output as the data output Q. If the logic_test signal does not indicate that a test mode is activated, then the multiplexer 56 can select the output from the latch 54 during a read function as the data output Q. Thus, the multiplexer 56 is inserted into the data output Q path to bypass the bitcell array 40 and asynchronously forward the inputted data D to the data output Q. The problem with such configuration is access time is not comparable to an actual read function of the memory device. Thus, timing of the data output Q from the data input D is independent of access time and does not provide an “at-speed” condition for testing of the downstream logic. Also, the use of a multiplexer for creating the data pass through creates an area penalty for implementing the multiplexer.
FIG. 2 illustrates a prior art memory device having a clocked write-through circuitry for testing the memory device. In order to address the access time, the sense amplifier 52's output can be coupled to a multiplexer 58 for selection to the latch 54. Another input of the multiplexer 58 can be coupled to the data signal D_T which is generated by the AND gate 44 for writing. The Logic_test signal can be used to select one of the inputs of the multiplexer 58 for output to the latch 54. The multiplexer 58 is thus added in the data output Q path to bypass the bitcell array 40 and synchronously forward the input data D to the data output Q. The drawback of such approach is that the downstream latch 54 is required to time the transition of the Q output appropriately. The use of the multiplexer 58 also still incurs some access time inaccuracy and area penalty in implementation of the multiplexer 58. Such solution provides for a nearly at-speed logic test attribute, but with performance and area overhead issues.
Therefore, there exists a need for an at-speed memory bypass function for a memory to handle test modes.